Circuit topology is critical to the study and use of electrical hardware. Circuit topology describes how circuit structures may be coupled together to ideally perform various electrical or logical functions within a circuit board or integrated chip. While many circuit topologies exist, one useful topology can be described as a voltage division topology. Voltage division topologies generally have one large voltage supply coupled to a plurality of descending interconnected operational elements, where the output voltage of one operational element is the input voltage of the next interconnected operational element. As a result of each operational element's resistance and performance of the designed function, a voltage division occurs and results in a decreased output voltage to power the next operational element. The operating voltage for a single operational element is the difference between the input voltage and the output voltage. The topology of the system voltage divider determines the absolute input and output voltage levels. The operating voltage of operational elements of the same circuit design in such a topology shall be the same within certain voltage variation limits. In such a system, each operational element is coupled to a system controller to ensure that voltage division across the circuit topology is working properly. The system controller manages the performance of each of the operational elements, therefore balancing current consumption per operational element and desired voltage division in the whole system. Due to the voltage division, each successive operational element will have a lower input and output voltage, while the operating voltage of operational elements of the same design should stay the same within in voltage variation limits.
Fully-depleted semiconductor-on-insulator (FD-SOI) PFET and NFET transistors include back gate terminals that can be used to influence the effective threshold voltage of the transistors by applying positive and negative voltages. Usually the positive voltages are larger than the operating voltage of these circuits. In one instance, positive voltages applied to the back-gate of NFETs and negative voltages applied to the back-gate of PFETs reduce the effective threshold voltage of both, which leads to a speed up of both devices.
The application of voltages to a back-gate in order to change the effective threshold voltage is called back-gate or body biasing (BB). Back-gate biasing is a design method that improves power, performance and area metrics of a circuit. However, back-gate biasing requires 1) a source for the positive voltages larger than the operating voltage, 2) a source for negative voltages, and 3) a voltage regulator to fine tune the positive and negative voltages such that the optimal effective threshold voltages for the circuits can be applied. In the prior art, positive and negative on-circuit charge pumps have been used as a source for 1) and 2), respectively, together with an on chip voltage regulator to serve 3). These charge pumps consume area and power on each circuit, reducing the power performance and area benefit provided by back-gate biasing. The power and area penalty of the charge pumps increases by the difference of the back-gate voltages compared to the available input operating voltage to the charge pump, such that for circuits with very low operating voltage (for instance 0.4V), the penalty of positive and negative back-gate bias voltages (e.g., 1.2V, −1.2V respectively) diminishes the advantage of back-gate bias for power performance and area considerably.